1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to distributed memory circuitry and methods for making the same.
2. Description of the Related Art
Most integrated circuit devices are required to have some type of memory device for storing information, and there is a growing trend to integrate embedded memory arrays directly onto the a chip, such as, a microprocessor, an application specific integrated circuit (ASIC), etc. Typically, when a memory device is embedded into a chip, the memory device (e.g., an Asynchronous SRAM) is provided with circuitry for writing and reading the data. By way of example, such common circuitry typically includes Y-decoders, X-decoders, sense amplifiers, output buffers, address transition detectors (ATD's) and clock buffers. Therefore, to produce a memory device that has fast access times and quick recoveries after a read/write operation, each of the components of the common circuitry must be tuned to eliminate delays or inefficiencies.
With this in mind, FIG. 1 shows a prior art block diagram of a memory 100 that is produced by a memory generator that may be embedded into an integrated circuit design. The memory 100 is shown having a memory array 102, which is the main memory array having a plurality of memory cells that are arranged in a row and column format. Typically, memory 100 is provided with a row decode 104, a column decode 106, control circuitry 105, an address transition detect (ATD) 110, and sense amplifiers and output buffers 107. It is these circuit components that are used to facilitate the writing and reading of data to or from selected cells in the memory array 102.
When the memory has an address transition detect (ATD) circuit 110, the memory is typically considered to be an asynchronous memory device. This is because the address transition detect (ATD) 110 will produce a clock input signal that is analogous to that produced by a synchronous memory device. By way of example, a synchronous memory device will have a "memory clock" signal that identifies a read or a write operation when a transition from LOW-to-HIGH (i.e., a rising edge) occurs, and commence a pre-charge operation when a transition from HIGH-to-LOW (i.e., a falling edge) occurs. As shown in a waveform 120, a time lapse between the falling edge and the next rising edge (i.e., when the next read or write operation occurs), is the time needed by the memory 100 to prepare itself for a next read or write operation. In this example, the ATD 110 is shown receiving an address transition input that provides information of when a memory address in the memory array 102 is to be accessed for a read or a write operation.
In prior art designs, the ATD 110 is also coupled to a clock buffer 112 that is well suited to provide a fixed amount of buffering/drive for a particular memory array 102. However, when the memory array 102 is replaced with a different size memory array, the clock buffer 112 will continue to produce the same fixed amount of drive (even though the load has changed). The possibility of interchanging different size memory arrays is not an uncommon occurrence. In fact, many companies implement what are known as core libraries, wherein the core libraries may include a plurality of memory arrays from which to pick an choose from. However, this increased flexibility may cause an integrated circuit design, e.g., a memory to be improperly matched for load. That is, the fixed clock buffer 112 that was well suited for use with the one size memory produced by a memory generator may not be well suited for a different size memory.
By way of example, if the new memory array is larger than the memory array that was previously produced by the memory generator, then there may be too little drive to compensate for the increased load. On the other hand, if the memory array 102 is replaced with a smaller sized memory array, then the fixed drive may be too large, thereby causing a slow down in the rate at which a read or a write operation may be performed. In either case, the clock buffer 112 of the memory 100 will also have to be replaced and tuned an increased cost each time the memory array 102 is modified. There are also tuning issues associated with the address transition circuitry, which is described in greater detail in a commonly assigned U.S. patent application having Ser. No. 08/928,713 (Attorney Docket Number ARTCP008), entitled "Self Adjusting Pre-Charge Delay in Memory Circuits and Methods for Making the Same," and filed on the same day as the instant patent application. This application is incorporated by reference herein.
In view of the foregoing, there is a need for a memory that has flexible clock buffer circuitry that may be distributed in response to a change in memory size.